12 search results - page 3 / 3 » Improved on-chip router analytical power and area modeling |
WCNC
2008
IEEE
13 years 11 months ago
2008
IEEE
Abstract—We examine the statistical distribution of the interference produced by a cluster of very many co-channel interferers, e.g., a sensor network, or a city full of active w...
MICRO
2007
IEEE
13 years 11 months ago
2007
IEEE
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...