23 search results - page 1 / 5 » Improving Balanced Scheduling with Compiler Optimizations th... |
PLDI
1995
ACM
13 years 8 months ago
1995
ACM
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
IJPP
2000
13 years 4 months ago
2000
Increases in instruction level parallelism are needed to exploit the potential parallelism available in future wide issue architectures. Predicated execution is an architectural m...
IEEEPACT
1999
IEEE
13 years 8 months ago
1999
IEEE
Increases in instruction level parallelism are needed to exploit the potential parallelism available in future wide issue architectures. Predicated execution is an architectural m...
LCTRTS
2007
Springer
13 years 10 months ago
2007
Springer
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
MICRO
2006
IEEE
13 years 10 months ago
2006
IEEE
The superblock is a scheduling region which exposes instruction level parallelism beyond the basic block through speculative execution of instructions. In general, scheduling supe...