8 search results - page 2 / 2 » Improving Data Cache Performance via Address Correlation: An... |
MICRO
2000
IEEE
13 years 9 months ago
2000
IEEE
Silent store instructions write values that exactly match the values that are already stored at the memory address that is being written. A recent study reveals that significant ...
LCTRTS
2007
Springer
13 years 11 months ago
2007
Springer
In the design of real-time and embedded systems, it is important to establish a bound on the worst-case execution time (WCET) of programs to assure via schedulability analysis tha...
VLDB
1999
ACM
13 years 9 months ago
1999
ACM
Recent high-performance processors employ sophisticated techniques to overlap and simultaneously execute multiple computation and memory operations. Intuitively, these techniques ...