10 search results - page 2 / 2 » Improving Energy Efficiency of Configurable Caches via Tempe... |
SAC
2008
ACM
13 years 4 months ago
2008
ACM
This paper proposes an address compression technique for load/store queue (LSQ) to improve the scalability and power efficiency. A load/store queue (LSQ) typically needs a fullyas...
ASPLOS
2008
ACM
13 years 6 months ago
2008
ACM
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industry. Most of the current research thrusts using chip multiprocessors (CMPs) as th...
JSAC
2008
13 years 4 months ago
2008
This paper addresses the multiplexing loss that occurs in relay networks due to causality of relays and the halfduplex constraint. We devise relay selection methods to recover the ...
SIGOPS
2010
12 years 11 months ago
2010
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
IOPADS
1996
13 years 5 months ago
1996
Many parallel scientific applications need high-performance I/O. Unfortunately, end-to-end parallel-I/O performance has not been able to keep up with substantial improvements in p...