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ASPLOS
2006
ACM
13 years 10 months ago
A spatial path scheduling algorithm for EDGE architectures
Growing on-chip wire delays are motivating architectural features that expose on-chip communication to the compiler. EDGE architectures are one example of communication-exposed mi...
Katherine E. Coons, Xia Chen, Doug Burger, Kathryn...
ASPLOS
2008
ACM
13 years 6 months ago
Optimistic parallelism benefits from data partitioning
Recent studies of irregular applications such as finite-element mesh generators and data-clustering codes have shown that these applications have a generalized data parallelism ar...
Milind Kulkarni, Keshav Pingali, Ganesh Ramanaraya...
DSL
1997
13 years 6 months ago
Experience with a Language for Writing Coherence Protocols
In this paper we describe our experience with Teapot [7], a domain-specific language for writing cache coherence protocols. Cache coherence is of concern when parallel and distrib...
Satish Chandra, James R. Larus, Michael Dahlin, Br...
IWMM
2009
Springer
152views Hardware» more  IWMM 2009»
13 years 11 months ago
A new approach to parallelising tracing algorithms
Tracing algorithms visit reachable nodes in a graph and are central to activities such as garbage collection, marshalling etc. Traditional sequential algorithms use a worklist, re...
Cosmin E. Oancea, Alan Mycroft, Stephen M. Watt