59 search results - page 2 / 12 » Improving Locality in Out-of-Core Computations Using Data La... |
VLSID
2002
IEEE
13 years 10 months ago
2002
IEEE
This paper introduces a dynamic layout optimization strategy to minimize the number of cycles spent in memory accesses in a cache-based memory environment. In this approach, a giv...
CC
2007
Springer
13 years 11 months ago
2007
Springer
As the amount of data used by programs increases due to the growth of hardware storage capacity and computing power, efficient memory usage becomes a key factor for performance. Si...
IEEEPACT
2009
IEEE
13 years 12 months ago
2009
IEEE
—With increasing numbers of cores, future CMPs (Chip Multi-Processors) are likely to have a tiled architecture with a portion of shared L2 cache on each tile and a bankinterleave...
EUC
2006
Springer
13 years 9 months ago
2006
Springer
As the ever-increasing gap between the speed of processor and the speed of memory has become the cause of one of primary bottlenecks of computer systems, modern architecture system...
EUROPAR
1998
Springer
13 years 9 months ago
1998
Springer
This paper aims to improve locality of references by suitably choosing array layouts. We use a new definition of spatial reuse vectors that takes into account memory layout of arra...