3 search results - page 1 / 1 » Improving instruction-level parallelism by loop unrolling an... |
MICRO
1995
IEEE
13 years 8 months ago
1995
IEEE
Exploitation ofinstruction-levelparallelism is an ejfective mechanism for improving the performance of modern super-scalar/VLIW processors. Various software techniques can be appl...
PLDI
1995
ACM
13 years 8 months ago
1995
ACM
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
MICRO
2000
IEEE
13 years 4 months ago
2000
IEEE
level of abstraction, compared with the program representation for scalar optimizations. For example, loop unrolling and loop unrolland-jam transformations exploit the large regist...