87 search results - page 3 / 18 » Improving the Memory Bandwidth Utilization Using Loop Transf... |
CGO
2003
IEEE
13 years 10 months ago
2003
IEEE
In this paper we present the internal representation and optimizations used by the CASH compiler for improving the memory parallelism of pointer-based programs. CASH uses an SSA-b...
PLDI
1994
ACM
13 years 9 months ago
1994
ACM
As microprocessor speeds increase, memory bandwidth is increasing y the performance bottleneck for microprocessors. This has occurred because innovation and technological improvem...
SAC
2002
ACM
13 years 5 months ago
2002
ACM
This paper presents a novel approach for the problem of generating tiled code for nested for-loops using a tiling transformation. Tiling or supernode transformation has been widel...
AVSS
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper presents the implementation of a video segmentation unit used for embedded automated video surveillance systems. Various aspects of the underlying segmentation algorith...
VLSID
2002
IEEE
13 years 10 months ago
2002
IEEE
This paper introduces a dynamic layout optimization strategy to minimize the number of cycles spent in memory accesses in a cache-based memory environment. In this approach, a giv...