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» Improving the Security of Dual-Rail Circuits
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CANS
2009
Springer
120views Cryptology» more  CANS 2009»
14 years 10 days ago
Improved Garbled Circuit Building Blocks and Applications to Auctions and Computing Minima
Abstract. We consider generic Garbled Circuit (GC)-based techniques for Secure Function Evaluation (SFE) in the semi-honest model. We describe efficient GC constructions for additi...
Vladimir Kolesnikov, Ahmad-Reza Sadeghi, Thomas Sc...
HOST
2009
IEEE
13 years 9 months ago
New Design Strategy for Improving Hardware Trojan Detection and Reducing Trojan Activation Time
Hardware Trojans in integrated circuits and systems have become serious concern to fabless semiconductor industry and government agencies in recent years. Most of the previously p...
Hassan Salmani, Mohammad Tehranipoor, Jim Plusquel...
IACR
2011
128views more  IACR 2011»
12 years 5 months ago
Sign Modules in Secure Arithmetic Circuits
In this paper, we study the complexity of secure multiparty computation using only the secure arithmetic black-box of a finite field, counting the cost by the number of secure m...
Ching-Hua Yu
CHES
2006
Springer
146views Cryptology» more  CHES 2006»
13 years 9 months ago
Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits
This paper presents a Path Swapping (PS) method which enables to enhance the security of Quasi Delay Insensitive Asynchronous Circuits against Power Analysis (PA) attack. This appr...
G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin
CASES
2010
ACM
13 years 3 months ago
Implementing virtual secure circuit using a custom-instruction approach
Although cryptographic algorithms are designed to resist at least thousands of years of cryptoanalysis, implementing them with either software or hardware usually leaks additional...
Zhimin Chen, Ambuj Sinha, Patrick Schaumont