24 search results - page 4 / 5 » Improving the Throughput of a Pipeline by Insertion of Delay... |
SPAA
1997
ACM
13 years 10 months ago
1997
ACM
Pipelining has been used in the design of many PRAM algorithms to reduce their asymptotic running time. Paul, Vishkin, and Wagener (PVW) used the approach in a parallel implementat...
ICS
2005
Tsinghua U.
13 years 11 months ago
2005
Tsinghua U.
With the increasing performance gap between the processor and the memory, the importance of caches is increasing for high performance processors. However, with reducing feature si...
HPCA
2008
IEEE
14 years 6 months ago
2008
IEEE
Simultaneous Multithreading (SMT) attempts to keep a dynamically scheduled processor's resources busy with work from multiple independent threads. Threads with longlatency st...
CHES
2006
Springer
13 years 10 months ago
2006
Springer
Balanced dynamic dual-rail gates and asynchronous circuits have been shown, if implemented correctly, to have natural and efficient resistance to side-channel attacks. Despite thei...
HPCA
2000
IEEE
13 years 10 months ago
2000
IEEE
This paper presents flit-reservation flow control, in which control flits traverse the network in advance of data flits, reserving buffers and channel bandwidth. Flit-reservation ...