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» In Situ Design of Register Operations
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ISVLSI
2008
IEEE
117views VLSI» more  ISVLSI 2008»
14 years 3 months ago
In Situ Design of Register Operations
We present methods to design programs or electronic circuits, for performing any operation on k registers of any sizes in a processor, in such a way that one uses no other working...
Serge Burckel, Emeric Gioan
JUCS
2010
154views more  JUCS 2010»
13 years 7 months ago
SimCon: A Tool to Support Rapid Evaluation of Smart Building Application Design using Context Simulation and Virtual Reality
: The promise of smart buildings (SBs) is a safer more productive environment for users and a more operationally efficient building for owners. The automation of building function ...
Kris McGlinn, Eleanor O'Neill, Alan Gibney, Declan...
DAC
2006
ACM
14 years 3 months ago
Visibility enhancement for silicon debug
Several emerging Design-for-Debug (DFD) methodologies are addressing silicon debug by making internal signal values and other data observable. Most of these methodologies require ...
Yu-Chin Hsu, Fur-Shing Tsai, Wells Jong, Ying-Tsai...
CSSE
2008
IEEE
14 years 3 months ago
Design and Implementation of the Virtual Machine Constructing on Register
: The technology of virtual machines is widely applied in many fields, such as code transplanting, cross-platform computing, and hardware simulation. The main purpose is to simulat...
Weibo Xie, Fu Ting
ITC
2000
IEEE
110views Hardware» more  ITC 2000»
14 years 1 months ago
Algorithm level re-computing with shifted operands-a register transfer level concurrent error detection technique
—This paper presents Algorithm-level REcomputing with Shifted Operands (ARESO), which is a new register transfer (RT) level time redundancy-based concurrent error detection (CED)...
Ramesh Karri, Kaijie Wu