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» Increasing Register File Immunity to Transient Errors
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CGO
2009
IEEE
14 years 5 days ago
ESoftCheck: Removal of Non-vital Checks for Fault Tolerance
—As semiconductor technology scales into the deep submicron regime the occurrence of transient or soft errors will increase. This will require new approaches to error detection. ...
Jing Yu, María Jesús Garzarán...
PDP
2011
IEEE
12 years 9 months ago
Quantifying Thread Vulnerability for Multicore Architectures
Abstract—Continuously reducing transistor sizes and aggressive low power operating modes employed by modern architectures tend to increase transient error rates. Concurrently, mu...
Isil Oz, Haluk Rahmi Topcuoglu, Mahmut T. Kandemir...