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» Increasing memory miss tolerance for SIMD cores
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2009
ACM
13 years 11 months ago
Increasing memory miss tolerance for SIMD cores
Manycore processors with wide SIMD cores are becoming a popular choice for the next generation of throughput oriented architectures. We introduce a hardware technique called “di...
David Tarjan, Jiayuan Meng, Kevin Skadron
CC
2008
Springer
144views System Software» more  CC 2008»
13 years 6 months ago
Control Flow Emulation on Tiled SIMD Architectures
Heterogeneous multi-core and streaming architectures such as the GPU, Cell, ClearSpeed, and Imagine processors have better power/ performance ratios and memory bandwidth than tradi...
Ghulam Lashari, Ondrej Lhoták, Michael McCo...
ISCA
2010
IEEE
185views Hardware» more  ISCA 2010»
13 years 10 months ago
Dynamic warp subdivision for integrated branch and memory divergence tolerance
SIMD organizations amortize the area and power of fetch, decode, and issue logic across multiple processing units in order to maximize throughput for a given area and power budget...
Jiayuan Meng, David Tarjan, Kevin Skadron
PPSC
2001
13 years 6 months ago
A Mathematical Cache Miss Analysis for Pointer Data Structures
As the gap between processor and memory performance widens, careful analyses and optimizations of cache memory behavior become increasingly important. While analysis of regular lo...
Hongli Zhang, Margaret Martonosi
CASES
2009
ACM
13 years 11 months ago
CheckerCore: enhancing an FPGA soft core to capture worst-case execution times
Embedded processors have become increasingly complex, resulting in variable execution behavior and reduced timing predictability. On such processors, safe timing specifications e...
Jin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Ta...