35 search results - page 1 / 7 » Inferring Finite-State Models with Temporal Constraints |
KBSE
2008
IEEE
13 years 11 months ago
2008
IEEE
Finite state machine-based abstractions of software behaviour are popular because they can be used as the basis for a wide range of (semi-) automated verification and validation ...
SIGSOFT
2009
ACM
14 years 5 months ago
2009
ACM
Many testing and analysis techniques use finite state models to validate and verify the quality of software systems. Since the specification of such models is complex and timecons...
JCST
2008
13 years 4 months ago
2008
Transformational approaches to generating design and implementation models from requirements can bring effectiveness and quality to software development. In this paper we present a...
EH
1999
IEEE
1999
IEEE
Evolvable Hardware or Learning Hardware? Induction of State Machines from Temporal Logic Constraints
13 years 9 months ago
Here we advocate an approach to learning hardware based on induction of finite state machines from temporal logic constraints. The method involves training on examples, constraint...
IJCAI
2003
13 years 6 months ago
2003
This paper addresses the formal verification of diagnosis systems. We tackle the problem of diagnosability: given a partially observable dynamic system, and a diagnosis system obs...