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» Input Queued Switches: Cell Switching vs. Packet Switching
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HOTI
2002
IEEE
13 years 11 months ago
A Four-Terabit Single-Stage Packet Switch with Large Round-Trip Time Support
We present the architecture and practical VLSI implementation of a 4-Tb/s single-stage switch. It is based on a combined input- and crosspoint-queued structure with virtual output...
François Abel, Cyriel Minkenberg, Ronald P....
FCCM
2006
IEEE
131views VLSI» more  FCCM 2006»
14 years 10 days ago
Packet Switched vs. Time Multiplexed FPGA Overlay Networks
— Dedicated, spatially configured FPGA interconnect is efficient for applications that require high throughput connections between processing elements (PEs) but with a limited ...
Nachiket Kapre, Nikil Mehta, Michael DeLorimier, R...
COMCOM
1999
122views more  COMCOM 1999»
13 years 6 months ago
An accurate performance model of shared buffer ATM switches under hot spot traffic
Asynchronous transfer mode (ATM) switches based on shared buffering are known to have better performance and buffer utilization than input or output queued switches. Shared buffer...
Mahmoud Saleh, Mohammed Atiquzzaman
INFOCOM
2003
IEEE
13 years 11 months ago
Using Switched Delay Lines for Exact Emulation of FIFO Multiplexers with Variable Length Bursts
—It has been studied extensively in the literature how one achieves exact emulation of First In First Out (FIFO) multiplexers for fixed size cells (or packets) using optical cro...
Cheng-Shang Chang, Duan-Shin Lee, Chao-Kai Tu
INFOCOM
2008
IEEE
14 years 21 days ago
Fair Scheduling through Packet Election
—In this paper, we consider the problem of designing scheduling algorithm for input queued switch that is both fair as well as throughput optimal. The significant body of litera...
Srikanth Jagabathula, Vishal Doshi, Devavrat Shah