59 search results - page 2 / 12 » Instruction Pre-Processing in Trace Processors |
MICRO
1999
IEEE
13 years 9 months ago
1999
IEEE
Branch mispredictions are a major obstacle to exploiting instruction-level parallelism, at least in part because all instructions after a mispredicted branch are squashed. However...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Modern Application Specific Instruction Set Processors (ASIPs) have customizable caches, where the size, associativity and line size can all be customized to suit a particular ap...
ISCAPDCS
2003
13 years 6 months ago
2003
Branch predictors and processor front-ends have been the focus of a number of computer architecture studies. Typically they are evaluated separately from other components using tr...
MICRO
1996
IEEE
13 years 9 months ago
1996
IEEE
As the issue widthof superscalar processors is increased, instructionfetch bandwidthrequirements will also increase. It will become necessary to fetch multiple basic blocks per cy...
MICRO
2000
IEEE
13 years 5 months ago
2000
IEEE
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...