138 search results - page 2 / 28 » Instruction Scheduling and Executable Editing |
MICRO
2003
IEEE
13 years 9 months ago
2003
IEEE
Ensuring back-to-back execution of dependent instructions in a conventional out-of-order processor requires scheduling logic that wakes up and selects instructions at the same rat...
IEEEPACT
1998
IEEE
13 years 8 months ago
1998
IEEE
Conventional speculative architectures use branch prediction to evaluate the most likely execution path during program execution. However, certain branches are difficult to predic...
HPCA
2004
IEEE
14 years 4 months ago
2004
IEEE
Modern microprocessors adopt speculative scheduling techniques where instructions are scheduled several clock cycles before they actually execute. Due to this scheduling delay, sc...
ISCA
2003
IEEE
13 years 9 months ago
2003
IEEE
To achieve high instruction throughput, instruction schedulers must be capable of producing high-quality schedules that maximize functional unit utilization while at the same time...
EUROPAR
2001
Springer
13 years 9 months ago
2001
Springer
Operand bypass logic might be one of the critical structures for future microprocessors to achieve high clock speed. The delay of the logic imposes the execution time budget to be ...