22 search results - page 1 / 5 » Instruction Scheduling with Release Times and Deadlines on I... |
RTCSA
2006
IEEE
13 years 11 months ago
2006
IEEE
ILP (Instruction Level Parallelism) processors are being increasingly used in embedded systems. In embedded systems, instructions may be subject to timing constraints. An optimisi...
RTSS
2002
IEEE
13 years 9 months ago
2002
IEEE
This paper presents a new workload model, called the state-dependent deadline model, for applications whose high-level timing requirements may change with time. The problem is how...
HPCA
2001
IEEE
14 years 5 months ago
2001
IEEE
Clustered ILP processors are characterized by a large number of non-centralized on-chip resources grouped into clusters. Traditional code generation schemes for these processors c...
ISCA
1997
IEEE
13 years 9 months ago
1997
IEEE
Current microprocessors aggressively exploit instructionlevel parallelism (ILP) through techniques such as multiple issue, dynamic scheduling, and non-blocking reads. Recent work ...
ASPLOS
1998
ACM
13 years 9 months ago
1998
ACM
Advances in VLSI technology will enable chips with over a billion transistors within the next decade. Unfortunately, the centralized-resource architectures of modern microprocesso...