22 search results - page 4 / 5 » Instruction Scheduling with Release Times and Deadlines on I... |
RTSS
2008
IEEE
14 years 4 days ago
2008
IEEE
Many embedded systems are subject to temporal constraints that require advance guarantees on meeting deadlines. Such systems rely on static analysis to safely bound worst-case exe...
ASAP
2004
IEEE
13 years 9 months ago
2004
IEEE
Large register file with multiple ports is a critical component of a high-performance processor. A large number of registers are necessary for processing a larger number of in-fli...
MICRO
1999
IEEE
13 years 10 months ago
1999
IEEE
Since there is generally insufficient instruction level parallelism within a single basic block, higher performance is achieved by speculatively scheduling operations in superbloc...
ICDCS
1995
IEEE
13 years 9 months ago
1995
IEEE
Tasks in a real-time application usually have several stringent timing, resource, and communication requirements. Designing a distributed computing system which can meet all these...
HPCA
2005
IEEE
14 years 6 months ago
2005
IEEE
A large multi-ported register file is indispensable for exploiting instruction level parallelism (ILP) in today's dynamically scheduled superscalar processors. The number of ...