15 search results - page 1 / 3 » Instruction Wake-Up in Wide Issue Superscalars |
EUROPAR
2001
Springer
13 years 10 months ago
2001
Springer
APCSAC
2005
IEEE
13 years 11 months ago
2005
IEEE
In order to enhance the performance of a computer, most modern processors use superscalar architecture and raise the clock frequency. Superscalar architecture can execute more than...
LCPC
2004
Springer
13 years 10 months ago
2004
Springer
Abstract. Branch predictors are associated with critical design issues for nowadays instruction greedy processors. We study two important domains where the optimization of decision...
IPPS
2000
IEEE
13 years 9 months ago
2000
IEEE
The instruction sets of general-purpose microprocessors are designed to offer good performance across a wide range of programs. The size and complexity of the instruction sets, how...
ISCA
1995
IEEE
13 years 9 months ago
1995
IEEE
Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be expl...