43 search results - page 3 / 9 » Instruction encoding synthesis for architecture exploration ... |
IISWC
2008
IEEE
13 years 11 months ago
2008
IEEE
The design and evaluation of microprocessor architectures is a difficult and time-consuming task. Although small, handcoded microbenchmarks can be used to accelerate performance e...
SAMOS
2010
Springer
13 years 3 months ago
2010
Springer
—Instruction set simulators (ISS) are vital tools for compiler and processor architecture design space exploration and verification. State-of-the-art simulators using just-in-ti...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
In this paper, we investigate the benefits of a flexible, application-specific instruction set by adding a run-time Reconfigurable Functional Unit (RFU) to a VLIW processor. Preli...
ICS
2007
Tsinghua U.
13 years 11 months ago
2007
Tsinghua U.
This paper explores the scalability of the Stream Processor architecture along the instruction-, data-, and thread-level parallelism dimensions. We develop detailed VLSI-cost and ...
DAC
2003
ACM
13 years 10 months ago
2003
ACM
Instruction set simulators are critical tools for the exploration and validation of new programmable architectures. Due to increasing complexity of the architectures and timeto-ma...