13 search results - page 1 / 3 » Instruction packing: reducing power and delay of the dynamic... |
ISLPED
2005
ACM
13 years 10 months ago
2005
ACM
The instruction scheduling logic used in modern superscalar microprocessors often relies on associative searching of the issue queue entries to dynamically wakeup instructions for...
PACS
2004
Springer
13 years 9 months ago
2004
Springer
Dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The delay ...
HPCA
2006
IEEE
14 years 4 months ago
2006
IEEE
We propose dynamic scheduler designs to improve the scheduler scalability and reduce its complexity in the SMT processors. Our first design is an adaptation of the recently propos...
ICCD
2005
IEEE
14 years 1 months ago
2005
IEEE
The dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The d...
GLVLSI
2010
IEEE
13 years 9 months ago
2010
IEEE
NBTI is one of the most important silicon reliability problems facing processor designers today. The impact of NBTI can be mitigated at both the circuit and microarchitecture leve...