27 search results - page 4 / 6 » Instruction set extension with shadow registers for configur... |
CSE
2008
IEEE
13 years 7 months ago
2008
IEEE
A well-known challenge during processor design is to obtain best possible results for a typical target application domain by combining flexibility and computational performance. A...
MICRO
1998
IEEE
13 years 10 months ago
1998
IEEE
Three dimensional (3D) graphics applications have become very important workloads running on today's computer systems. A cost-effective graphics solution is to perform geomet...
MICRO
1993
IEEE
13 years 10 months ago
1993
IEEE
The conventional classification of inter-instruction dependencies (data, anti and output dependencies) provides a basic scheme for the analysis of pipeline hazards in pipelined in...
ICCAD
2001
IEEE
14 years 2 months ago
2001
IEEE
In this paper we describe a software pipelining framework, CALiBeR (Cluster Aware Load Balancing Retiming Algorithm), suitable for compilers targeting clustered embedded VLIW proc...
ASPLOS
2009
ACM
14 years 6 months ago
2009
ACM
Parallel bit stream algorithms exploit the SWAR (SIMD within a register) capabilities of commodity processors in high-performance text processing applications such as UTF8 to UTF-...