32 search results - page 1 / 7 » Instruction trace compression for rapid instruction cache si... |
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Modern Application Specific Instruction Set Processors (ASIPs) have customizable caches, where the size, associativity and line size can all be customized to suit a particular ap...
ISCAPDCS
2003
13 years 6 months ago
2003
Branch predictors and processor front-ends have been the focus of a number of computer architecture studies. Typically they are evaluated separately from other components using tr...
CASES
2001
ACM
13 years 9 months ago
2001
ACM
Abstract. Existing variable-length instruction formats provide higher code densities than fixed-length formats, but are ill-suited to pipelined or parallel instruction fetch and de...
MICRO
2000
IEEE
13 years 9 months ago
2000
IEEE
Dynamic Zero Compression reduces the energy required for cache accesses by only writing and reading a single bit for every zero-valued byte. This energy-conscious compression is i...
IEEEPACT
1999
IEEE
13 years 9 months ago
1999
IEEE
Trace cache, an instruction fetch technique that reduces taken branch penalties by storing and fetching program instructions in dynamic execution order, dramatically improves inst...