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» Integer mapping architectures for the polynomial ring engine
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ARITH
1993
IEEE
13 years 10 months ago
Integer mapping architectures for the polynomial ring engine
S. S. Bizzan, Graham A. Jullien, Neil M. Wigley, W...
ASAP
1995
IEEE
145views Hardware» more  ASAP 1995»
13 years 9 months ago
An array processor for inner product computations using a Fermat number ALU
This paper explores an architecture for parallel independent computations of inner products over the direct product ring . The structure is based on the polynomial mapping of the ...
Wenzhe Luo, Graham A. Jullien, Neil M. Wigley, Wil...
DAC
2003
ACM
14 years 6 months ago
Optimal integer delay budgeting on directed acyclic graphs
Delay budget is an excess delay each component of a design can tolerate under a given timing constraint. Delay budgeting has been widely exploited to improve the design quality. W...
Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahas...
VLSID
2002
IEEE
98views VLSI» more  VLSID 2002»
14 years 6 months ago
On Test Scheduling for Core-Based SOCs
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
Sandeep Koranne
EMSOFT
2006
Springer
13 years 9 months ago
New approach to architectural synthesis: incorporating QoS constraint
Embedded applications like video decoding, video streaming and those in the network domain, typically have a Quality of Service (QoS) requirement which needs to be met. Apart from...
Harsh Dhand, Basant Kumar Dwivedi, M. Balakrishnan