10 search results - page 1 / 2 » Integrating Formal Verification Methods with A Conventional ... |
DAC
1996
ACM
13 years 8 months ago
1996
ACM
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
DAC
2009
ACM
13 years 11 months ago
2009
ACM
The latest advancements in the commercial formal model checkers have enabled the integration of formal property verification with the conventional testbench based methods in the o...
FORTE
1994
13 years 5 months ago
1994
The record of successful applications of formal verification techniques is slowly growing. Our ultimate aim, however, is not to perform small pilot projects that show that verific...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
Recently a lot of multimedia applications are emerging on portable appliances. They require both the flexibility of upgradeable devices (traditionally software based) and a powerf...
TII
2008
13 years 4 months ago
2008
Abstract--Safety analysis in Systems Engineering (SE) processes, as usually implemented, rarely relies on formal methods such as model checking since such techniques, however power...