27 search results - page 3 / 6 » Integrating the Specification Techniques of Graph Transforma... |
CPAIOR
2006
Springer
13 years 9 months ago
2006
Springer
Temporal planning (TP) is notoriously difficult because it requires to solve a propositional STRIPS planning problem with temporal constraints. In this paper, we propose an efficie...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
In this paper, we propose a new methodology to integrate circuit transformation into routing. More specifically, this paper shows an approach for performing routing and wire recon...
ASE
2005
13 years 5 months ago
2005
Techniques for efficiently evaluating future time Linear Temporal Logic (abbreviated LTL) formulae on finite execution traces are presented. While the standard models of LTL are i...
TABLEAUX
1998
Springer
13 years 9 months ago
1998
Springer
ple (Extended Abstract) Edmund M. Clarke and Sergey Berezin Carnegie Mellon University -- USA Model checking is an automatic verification technique for finite state concurrent syst...
DAC
2001
ACM
14 years 6 months ago
2001
ACM
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuit...