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ICRA
1993
IEEE
99views Robotics» more  ICRA 1993»
13 years 8 months ago
Integration of Reactive Navigation with a flexible Parallel Hardware Architecture
To demonstrate the flexibility and portability of both a schema-based software architecture and a message-passing hardware architecture, the two were integrated within a very shor...
Thomas R. Collins, Ronald C. Arkin, Andrew M. Hens...
ASPDAC
1995
ACM
77views Hardware» more  ASPDAC 1995»
13 years 8 months ago
A scheduling algorithm for synthesis of bus-partitioned architectures
- Due to efficient interconnect structure and internal parallelism bus-partitioned architectures are very beneficial for sub-micron chip design. This paper presents a new approach ...
Vasily G. Moshnyaga, Fumiaki Ohbayashi, Keikichi T...
ISCAS
2007
IEEE
105views Hardware» more  ISCAS 2007»
13 years 10 months ago
Parallel current-steering D/A Converters for Flexibility and Smartness
—This paper presents a DAC architecture built on parallel current-steering sub-DAC entities. Two main novelties are explored: flexibility and smartness. Firstly, a number of avai...
Georgi I. Radulov, Patrick J. Quinn, Pieter Harpe,...
HPCA
2008
IEEE
14 years 4 months ago
An OS-based alternative to full hardware coherence on tiled CMPs
The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling...
Christian Fensch, Marcelo Cintra
TC
2010
13 years 2 months ago
Network-on-Chip Hardware Accelerators for Biological Sequence Alignment
—The most pervasive compute operation carried out in almost all bioinformatics applications is pairwise sequence homology detection (or sequence alignment). Due to exponentially ...
Souradip Sarkar, Gaurav Ramesh Kulkarni, Partha Pr...