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HPCA
2001
IEEE
14 years 5 months ago
Reducing DRAM Latencies with an Integrated Memory Hierarchy Design
In this papel; we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory syst...
Wei-Fen Lin, Steven K. Reinhardt, Doug Burger
ICS
2005
Tsinghua U.
13 years 10 months ago
A heterogeneously segmented cache architecture for a packet forwarding engine
As network traffic continues to increase and with the requirement to process packets at line rates, high performance routers need to forward millions of packets every second. Eve...
Kaushik Rajan, Ramaswamy Govindarajan
MSWIM
2005
ACM
13 years 10 months ago
Content and service replication strategies in multi-hop wireless mesh networks
Emerging multi-hop wireless mesh networks have much different characteristics than the Internet. They have low dimensionality and large diameters. Content and service replication ...
Shudong Jin, Limin Wang
ICDCS
2008
IEEE
13 years 11 months ago
PFC: Transparent Optimization of Existing Prefetching Strategies for Multi-Level Storage Systems
The multi-level storage architecture has been widely adopted in servers and data centers. However, while prefetching has been shown as a crucial technique to exploit the sequentia...
Zhe Zhang, Kyuhyung Lee, Xiaosong Ma, Yuanyuan Zho...