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» Interconnect Analysis: From 3-D Structures to Circuit Models
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DAC
2006
ACM
14 years 6 months ago
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several othe...
Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sh...
CVPR
2000
IEEE
14 years 7 months ago
Integrated 3D Scene Flow and Structure Recovery from Multiview Image Sequences
Scene ow is the 3D motion eld of points in the world. Given N (N > 1) image sequences gather ed with a N-eye stereo camera or N calibrated cameras, we present a novel system wh...
Ye Zhang, Chandra Kambhamettu
ICCAD
2004
IEEE
138views Hardware» more  ICCAD 2004»
14 years 2 months ago
A thermal-driven floorplanning algorithm for 3D ICs
As the technology progresses, interconnect delays have become bottlenecks of chip performance. Three dimensional (3D) integrated circuits are proposed as one way to address this p...
Jason Cong, Jie Wei, Yan Zhang
BMCBI
2004
208views more  BMCBI 2004»
13 years 5 months ago
Using 3D Hidden Markov Models that explicitly represent spatial coordinates to model and compare protein structures
Background: Hidden Markov Models (HMMs) have proven very useful in computational biology for such applications as sequence pattern matching, gene-finding, and structure prediction...
Vadim Alexandrov, Mark Gerstein
TOG
2008
291views more  TOG 2008»
13 years 5 months ago
Interactive 3D architectural modeling from unordered photo collections
We present an interactive system for generating photorealistic, textured, piecewise-planar 3D models of architectural structures and urban scenes from unordered sets of photograph...
Sudipta N. Sinha, Drew Steedly, Richard Szeliski, ...