3 search results - page 1 / 1 » Interconnect Delay Minimization Using a Novel Pre-Mid-Post B... |
VLSID
2003
IEEE
14 years 5 months ago
2003
IEEE
We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI circuit.The problem can be restated as a combined buffer insertion, buffer siz...
ICCAD
1997
IEEE
13 years 8 months ago
1997
IEEE
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
GLVLSI
2009
IEEE
13 years 11 months ago
2009
IEEE
In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a...