154 search results - page 1 / 31 » Interconnect Optimization Strategies for High-Performance VL... |
VLSID
1999
IEEE
13 years 8 months ago
1999
IEEE
Interconnect tuning and repeater insertion are necessary to optimize interconnectdelay, signalperformanceandintegrity, andinterconnectmanufacturability and reliability. Repeater i...
DATE
1998
IEEE
13 years 8 months ago
1998
IEEE
Interconnect tuning is an increasingly critical degree of freedom in the physical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of lin...
ICCCN
2008
IEEE
13 years 10 months ago
2008
IEEE
—Understanding the communication behavior and network resource usage of parallel applications is critical to achieving high performance and scalability on systems with tens of th...
ASPDAC
2011
ACM
12 years 8 months ago
2011
ACM
3-D monolithic integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. Since the device layers are processed in sequent...
VLSID
2003
IEEE
14 years 4 months ago
2003
IEEE
We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI circuit.The problem can be restated as a combined buffer insertion, buffer siz...