27 search results - page 6 / 6 » Interconnect capacitance estimation for FPGAs |
ICCAD
2006
IEEE
14 years 2 months ago
2006
IEEE
Most existing buffering algorithms neglect the impact of inductance on circuit performance, which causes large error in circuit analysis and optimization. Even for the approaches...
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...