34 search results - page 1 / 7 » Interconnect power and delay optimization by dynamic program... |
ISPD
2010
ACM
13 years 11 months ago
2010
ACM
VLSID
2003
IEEE
14 years 4 months ago
2003
IEEE
In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number ofconstraints. By intr...
TVLSI
2002
13 years 4 months ago
2002
Abstract--The design of high integrity, area efficient power distribution grids has become of practical importance as the portion of on-chip interconnect resources dedicated to pow...
VLSID
1999
IEEE
13 years 8 months ago
1999
IEEE
Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which e...
ICCAD
1996
IEEE
13 years 8 months ago
1996
IEEE
In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We de ne a class of optimization problems as CH-posynomial programs and reveal a genera...