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IPPS
2002
IEEE
13 years 8 months ago
JPG - A Partial Bitstream Generation Tool to Support Partial Reconfiguration in Virtex FPGAs
Reconfigurable computing based on partial reconfiguration of field programmable gate arrays (FPGAs) is yet to move to the mainstream of computing. Hardware devices that support su...
Anup Kumar Raghavan, Peter Sutton
ARCS
2006
Springer
13 years 7 months ago
Combitgen: A new approach for creating partial bitstreams in Virtex-II Pro
Today's FPGAs (Field Programmable Gate Arrays) are widely used, but not to their full potential. In Virtex series FPGAs from Xilinx a special feature, the dynamic and partial...
Christopher Claus, Florian Helmut Müller, Wal...
FPL
2004
Springer
87views Hardware» more  FPL 2004»
13 years 9 months ago
Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs
This paper presents an innovative way to deploy Bitstream Intellectual Property (BIP) cores. By using standard tools to generate bitstreams for Field Programmable Gate Arrays (FPGA...
Edson L. Horta, John W. Lockwood
IPPS
2007
IEEE
13 years 10 months ago
A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration
The Xilinx Virtex family of FPGAs provides the ability to perform partial run-time reconfiguration, also known as dynamic partial reconfiguration (DPR). Taking this concept one st...
Christopher Claus, Florian Helmut Müller, Joh...
FPL
2007
Springer
125views Hardware» more  FPL 2007»
13 years 9 months ago
Run-time Partial Reconfiguration for Removal, Placement and Routing on the Virtex-II-Pro
Reconfigurable computing entails the utilization of a generalpurpose processor augmented with a reconfigurable hardware structure (usually an FPGA). Normally, a complete recon...
Stefan Raaijmakers, Stephan Wong