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» K2: an estimator for peak sustainable power of VLSI circuits
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ISLPED
1997
ACM
130views Hardware» more  ISLPED 1997»
13 years 7 months ago
K2: an estimator for peak sustainable power of VLSI circuits
New measures of peak power in the context of sequential circuits are proposed. This paper presents an automatic procedure to obtain very good lower bounds on these measures as wel...
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. P...
DATE
1999
IEEE
118views Hardware» more  DATE 1999»
13 years 8 months ago
Peak Power Estimation Using Genetic Spot Optimization for Large VLSI Circuits
Estimating peak power involves optimization of the circuit's switching function. We propose genetic spot expansion and optimization in this paper to estimate tight peak power...
Michael S. Hsiao
ISQED
2009
IEEE
133views Hardware» more  ISQED 2009»
13 years 10 months ago
A novel ACO-based pattern generation for peak power estimation in VLSI circuits
Estimation of maximal power consumption is an essential task in VLSI circuit realizations since power value significantly affects the reliability of the circuits. The key issue o...
Yi-Ling Liu, Chun-Yao Wang, Yung-Chih Chen, Ya-Hsi...
GLVLSI
2007
IEEE
158views VLSI» more  GLVLSI 2007»
13 years 5 months ago
RT-level vector selection for realistic peak power simulation
We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with ...
Chia-Chien Weng, Ching-Shang Yang, Shi-Yu Huang
GLVLSI
2003
IEEE
119views VLSI» more  GLVLSI 2003»
13 years 9 months ago
Simultaneous peak and average power minimization during datapath scheduling for DSP processors
The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using...
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappi...