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TCAD
1998
82views more  TCAD 1998»
13 years 3 months ago
LOT: Logic Optimization with Testability. New transformations for logic synthesis
—A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random...
Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang K...
ICCAD
1995
IEEE
88views Hardware» more  ICCAD 1995»
13 years 7 months ago
LOT: logic optimization with testability-new transformations using recursive learning
: A new approach to optimize multi-level logic circuits is introduced. Given a multi-level circuit, the synthesis method optimizes its area, simultaneously enhancing its random pat...
Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang K...
DAC
1997
ACM
13 years 7 months ago
Technology-Dependent Transformations for Low-Power Synthesis
We propose a methodology for applying gate-level logic transformations to optimize power in digital circuits. Statistically simulated[14] switching information, gate delays, signa...
Rajendran Panda, Farid N. Najm
INTEGRATION
2008
87views more  INTEGRATION 2008»
13 years 3 months ago
SafeResynth: A new technique for physical synthesis
Physical synthesis is a relatively young field in Electronic Design Automation. Many published optimizations for physical synthesis end up hurting the quality of the final design,...
Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
ISLPED
1995
ACM
70views Hardware» more  ISLPED 1995»
13 years 7 months ago
Transformation and synthesis of FSMs for low-power gated-clock implementation
We present a technique that automatically synthesizes nite state machines with gated clocks to reduce the power dissipation of the nal implementation. We describe a new transfor...
Luca Benini, Giovanni De Micheli