8 search results - page 1 / 2 » Latency-Guided On-Chip Bus Network Design |
ICCAD
2000
IEEE
13 years 9 months ago
2000
IEEE
Abstract— Deep submicron technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in...
DAC
2001
ACM
14 years 5 months ago
2001
ACM
Milenko Drinic UCLA Computer Science Dep. 4732 Boelter Hall Los Angeles, CA 90095-1596 milenko@cs.ucla.edu Darko Kirovski Microsoft Research One Microsoft Way Redmond, WA 98052 da...
SLIP
2006
ACM
13 years 10 months ago
2006
ACM
— The increasing gap between design productivity and chip complexity and the emerging Systems-On-Chip (SOC) architectural template have led to the wide utilization of reusable ha...
VLSID
2002
IEEE
14 years 4 months ago
2002
IEEE
Interconnection networks in Systems-On-Chip begin to have a non-negligible impact on the power consumption of a whole system. This is because of increasing inter-wire capacitances...
INTEGRATION
2008
13 years 4 months ago
2008
With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor SystemsOn-Chip (MPSoCs) consisting of complex integrated component...