248 search results - page 1 / 50 » Layered Switching for Networks on Chip |
DAC
2007
ACM
14 years 5 months ago
2007
ACM
We present and evaluate a novel switching mechanism called layered switching. Conceptually, the layered switching implements wormhole on top of virtual cut-through switching. To s...
DFT
2009
IEEE
13 years 11 months ago
2009
IEEE
We propose a framework that allows dual-layer cooperative error control in a nanoscale network-on-chip (NoC), to simultaneously improve reliability, performance and energy efficie...
ISVLSI
2002
IEEE
13 years 9 months ago
2002
IEEE
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NO...
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
— Three-dimensional die stacking integration provides the ability to stack multiple layers of processed silicon with a large number of vertical interconnects. Through Silicon Via...
3DIC
2009
IEEE
13 years 11 months ago
2009
IEEE
—The physical performance of a 3-Dimensional Network-on-Chip (NoC) mesh architecture employing Through Silicon Vias (TSV) for vertical connectivity is investigated with a cycle-a...