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» Layout Driven Logic Synthesis for FPGAs
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DAC
1994
ACM
9 years 7 months ago
Layout Driven Logic Synthesis for FPGAs
Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, ...
FPL
2004
Springer
90views Hardware» more  FPL 2004»
9 years 9 months ago
Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis
Abstract. Layout tools for FPGAs can typically be run in two different modes: non-timing-driven and timing-driven. Non-timing-driven mode produces a solution quickly, without consi...
Jason Helge Anderson, Sudip Nag, Kamal Chaudhary, ...
ICCAD
2001
IEEE
111views Hardware» more  ICCAD 2001»
10 years 18 days ago
Congestion Aware Layout Driven Logic Synthesis
In this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. In addition, we employ partitionin...
Thomas Kutzschebauch, Leon Stok
ICCAD
1991
IEEE
100views Hardware» more  ICCAD 1991»
9 years 7 months ago
Layout Driven Logic Restructuring/Decomposition
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
Massoud Pedram, Narasimha B. Bhat
FPGA
2014
ACM
108views FPGA» more  FPGA 2014»
4 years 10 months ago
Fast and effective placement and routing directed high-level synthesis for FPGAs
Achievable frequency (fmax) is a widely used input constraint for designs targeting Field-Programmable Gate Arrays (FPGA), because of its impact on design latency and throughput. ...
Hongbin Zheng, Swathi T. Gurumani, Kyle Rupnow, De...
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