6 search results - page 1 / 2 » Layout Driven Logic Synthesis for FPGAs |
DAC
1994
ACM
13 years 8 months ago
1994
ACM
FPL
2004
Springer
13 years 9 months ago
2004
Springer
Abstract. Layout tools for FPGAs can typically be run in two different modes: non-timing-driven and timing-driven. Non-timing-driven mode produces a solution quickly, without consi...
ICCAD
2001
IEEE
14 years 1 months ago
2001
IEEE
In this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. In addition, we employ partitionin...
ICCAD
1991
IEEE
13 years 7 months ago
1991
IEEE
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
FCCM
2011
IEEE
12 years 8 months ago
2011
IEEE
— Recent progress in High-Level Synthesis (HLS) es has helped raise the abstraction level of FPGA programming. However implementation and performance evaluation of the HLS-genera...