2 search results - page 1 / 1 » Layout Techniques for Minimizing On-Chip Interconnect Self I... |
DAC
1998
ACM
14 years 5 months ago
1998
ACM
Because magnetic e ects have a much longer spatial range than electrostatic e ects, an interconnect line with large inductance will be sensitive to distant variations in interconn...
VLSID
2000
IEEE
13 years 9 months ago
2000
IEEE
The test signal method can be used to measure and model inductance parameters (self and mutual) of a very small interconnect especially in highdensity IC’s by using a test signa...