3 search results - page 1 / 1 » Leakage current starved domino logic |
GLVLSI
2006
IEEE
13 years 10 months ago
2006
IEEE
A new circuit technique based on a single PMOS sleep transistor and a dual threshold voltage CMOS technology is proposed in this paper for simultaneously reducing subthreshold and...
ISQED
2006
IEEE
13 years 10 months ago
2006
IEEE
- A low overhead circuit technique is proposed in this paper for simultaneously reducing subthreshold and gate oxide leakage currents in domino logic circuits. PMOS sleep transisto...
GLVLSI
2002
IEEE
13 years 9 months ago
2002
IEEE
A low swing domino logic technique is proposed to decrease power consumption without sacrificing noise immunity. With the proposed low swing domino logic circuit technique, active...