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» Linear Network Codes and Systems of Polynomial Equations
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FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
13 years 5 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek
GLOBECOM
2007
IEEE
13 years 11 months ago
A Distributed Approach to Interference Cancellation
Abstract—In this paper1, we propose and analyze a novel idea of performing interference cancellation (IC) in a distributed/cooperative manner, with a motivation to provide multiu...
K. Raghu, Saif K. Mohammed, Ananthanarayanan Chock...
SAMOS
2004
Springer
13 years 10 months ago
Scalable Instruction-Level Parallelism.
This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves ...
Chris R. Jesshope