141 search results - page 1 / 29 » Load Execution Latency Reduction |
ICS
1998
Tsinghua U.
13 years 9 months ago
1998
Tsinghua U.
In order to achieve high performance, contemporary microprocessors must effectively process the four major instruction types: ALU, branch, load, and store instructions. This paper...
EUROPAR
2001
Springer
13 years 9 months ago
2001
Springer
Operand bypass logic might be one of the critical structures for future microprocessors to achieve high clock speed. The delay of the logic imposes the execution time budget to be ...
MICRO
1995
IEEE
13 years 8 months ago
1995
IEEE
Untolerated load instruction latencies often have a significant impact on overall program performance. As one means of mitigating this effect, we present an aggressive hardware-b...
HPCA
2002
IEEE
14 years 5 months ago
2002
IEEE
This paper explores the concept of micro-architectural loops and discusses their impact on processor pipelines. In particular, we establish the relationship between loose loops an...
CLUSTER
2009
IEEE
13 years 9 months ago
2009
IEEE
—Achieving high-performance message passing on top of generic ETHERNET hardware suffers from the NIC interruptdriven model where coalescing is usually involved. We present an in-...