141 search results - page 2 / 29 » Load Execution Latency Reduction |
EUROPAR
2001
Springer
13 years 10 months ago
2001
Springer
Optimizations performed at link time or directly applied to nal program executables have received increased attention in recent years. This paper discuss the discovery and elimina...
ISCA
2005
IEEE
13 years 11 months ago
2005
IEEE
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
APCSAC
2003
IEEE
13 years 10 months ago
2003
IEEE
Virtual multicasting (VMC) combines some of the benefits of caching (transparency, dynamic adaptation to workload) and multicasting (reducing duplicated traffic). Virtual multicas...
ISCA
2005
IEEE
13 years 11 months ago
2005
IEEE
The load-store unit is a performance critical component of a dynamically-scheduled processor. It is also a complex and non-scalable component. Several recently proposed techniques...
HPCA
1999
IEEE
13 years 9 months ago
1999
IEEE
This work presents and evaluates a novel processor microarchitecture which combines two paradigms: access/ execute decoupling and simultaneous multithreading. We investigate how b...