3 search results - page 1 / 1 » Localized On-Chip Power Delivery Network Optimization via Se... |
ISQED
2006
IEEE
13 years 10 months ago
2006
IEEE
— In this paper, we propose an efficient algorithm to reduce the voltage noises for on-chip power/ground (P/G) networks of VLSI. The new method is based on the sequence of linea...
DAC
1999
ACM
14 years 5 months ago
1999
ACM
ICCD
2007
IEEE
14 years 1 months ago
2007
IEEE
In this paper, we propose a novel on-chip voltage drop reduction technique for on-chip power delivery networks of VLSI systems in the presence of variational leakage current sourc...