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» Localized microarchitecture-level voltage management
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ISCAS
2006
IEEE
119views Hardware» more  ISCAS 2006»
13 years 10 months ago
Localized microarchitecture-level voltage management
— Diminishing voltage margins, coupled with power and temperature constraints, call for microarchitecture-level runtime mechanisms for voltage control. This paper describes a loc...
YongKang Zhu, David H. Albonesi
ISLPED
2004
ACM
110views Hardware» more  ISLPED 2004»
13 years 9 months ago
Reducing pipeline energy demands with local DVS and dynamic retiming
The quadratic relationship between voltage and energy has made dynamic voltage scaling (DVS) one of the most powerful techniques to reduce system power demands. Recently, techniqu...
Seokwoo Lee, Shidhartha Das, Toan Pham, Todd M. Au...
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
13 years 10 months ago
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Power delivery is a growing reliability concern in microprocessors as the industry moves toward feature-rich, powerhungrier designs. To battle the ever-aggravating power consumpti...
Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hs...
ISCA
2003
IEEE
168views Hardware» more  ISCA 2003»
13 years 9 months ago
Temperature-Aware Microarchitecture
With power density and hence cooling costs rising exponentially, processor packaging can no longer be designed for the worst case, and there is an urgent need for runtime processo...
Kevin Skadron, Mircea R. Stan, Wei Huang, Sivakuma...
SIGMETRICS
2010
ACM
162views Hardware» more  SIGMETRICS 2010»
13 years 9 months ago
Coordinated power management of voltage islands in CMPs
Multiple clock domain architectures have recently been proposed to alleviate the power problem in CMPs by having different frequency/voltage values assigned to each domain based o...
Asit K. Mishra, Shekhar Srikantaiah, Mahmut T. Kan...