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» Logic Design Considerations for 0.5-Volt CMOS
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ARVLSI
2001
IEEE
305views VLSI» more  ARVLSI 2001»
13 years 7 months ago
Logic Design Considerations for 0.5-Volt CMOS
As the operating supply voltage for commercial CMOS devices falls below 2 V, research activities are underway to develop CMOS integrated circuits that can operate at supply voltag...
K. Joseph Hass, Jack Venbrux, Prakash Bhatia
ARVLSI
2001
IEEE
289views VLSI» more  ARVLSI 2001»
13 years 7 months ago
A High-Performance 64-bit Adder Implemented in Output Prediction Logic
Output Prediction Logic (OPL) is a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the ...
Sheng Sun, Larry McMurchie, Carl Sechen
GLVLSI
1999
IEEE
88views VLSI» more  GLVLSI 1999»
13 years 8 months ago
Logic in Wire: Using Quantum Dots to Implement a Microprocessor
Despite the seemingly endless upwards spiral of modern VLSI technology, many experts are predicting a hard wall for CMOS in about a decade. Given this, researchers continue to loo...
Michael T. Niemier, Peter M. Kogge
DAC
2006
ACM
14 years 4 months ago
NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture
Recent progress on nanodevices, such as carbon nanotubes and nanowires, points to promising directions for future circuit design. However, nanofabrication techniques are not yet m...
Wei Zhang, Niraj K. Jha, Li Shang
VLSID
2006
IEEE
169views VLSI» more  VLSID 2006»
13 years 9 months ago
A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology
As the IC process technology scales, the oxide thickness and operating voltage continues to decrease. The gate oxide thickness in recent and future IC process technology has appro...
Sanjeev K. Jain, Pankaj Agarwal