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» Logic Simulation Using Networks of State Machines
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VLSID
1997
IEEE
98views VLSI» more  VLSID 1997»
13 years 9 months ago
Synthesis for Logical Initializability of Synchronous Finite State Machines
—Logical initializability is the property of a gate-level circuit whereby it can be driven to a unique start state when simulated by a three-valued (0, 1, ) simulator. In practic...
Montek Singh, Steven M. Nowick
ICML
2009
IEEE
14 years 5 months ago
Proto-predictive representation of states with simple recurrent temporal-difference networks
We propose a new neural network architecture, called Simple Recurrent Temporal-Difference Networks (SR-TDNs), that learns to predict future observations in partially observable en...
Takaki Makino
DAC
2002
ACM
14 years 5 months ago
Software synthesis from synchronous specifications using logic simulation techniques
This paper addresses the problem of automatic generation of implementation software from high-level functional specifications in the context of embedded system on chip designs. So...
Yunjian Jiang, Robert K. Brayton