This paper presents a system for recognizing sketched logic circuits in real-time and graphically simulating them afterwords. It has been developed for use in university and school...
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
This paper presents a framework for interactive applications running in a lecture recording system using the board as interface metaphor. A number of such applications, called Cha...
Designing modern circuits comprised of millions of gates is a very challenging task. Therefore new directions are investigated for efficient modeling and verification of such syst...